This application relies for priority upon Korean Patent Application No. 2000-64056, filed on Oct. 30, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention relates generally to dynamic random access memory (DRAM) devices, and more particularly to a sub word line drive circuit of the DRAM device.
FIG. 1 shows a layout of a conventional dynamic random access memory (DRAM) device. Referring to FIG. 1, a DRAM device is formed of a plurality of sub arrays 10 arranged with rows and columns. Each of the sub arrays 10 includes a plurality of word lines W/L, a plurality of bit line pairs BL and BLB, and a plurality of memory cells MC arranged on intersection regions of the word lines W/L and the bit line pairs BL and BLB. Sense amplification regions 20 are disposed between the sub arrays 10 in the row direction. Each of the sense amplification regions 20 includes a plurality of sense amplifiers connected to the bit line pairs BL and BLB, which extend in the row direction. As is well known to those skilled in the art, the sense amplifiers of the sense amplification regions 20 are shared with the adjacent sub arrays 10.
Continuing to refer to FIG. 1, sub word line drive regions 30 are disposed between the sub arrays 10 in the column direction. Each of the sub word line drive regions 30 includes a plurality of sub word line drivers SWD. A portion of the word lines W/L are selected by the sub word line drivers SWD of the sub word line drive regions 30 disposed on one side of the sub arrays 10. The rest of the word lines W/L are selected by the sub word line drivers SWD of sub word line drive regions 30 disposed on the other side. Each of the sub word line drivers SWD selects a corresponding sub word line W/L in response to the word line signals WLE provided from a main word line (or global word line) WLEi (where i=0xcx9cn, and n is a positive integer greater than 1) connected to a main word decoder 50, and a word line drive signal PXIj (where j=0xcx9c3) provided from a word line drive circuit (not shown). Conjunction regions 40 are disposed between the sub word line drive regions 30 in the row direction.
FIG. 2 is a circuit diagram showing the prior art sub word line driver SWD of FIG. 1. Referring to FIG. 2, the conventional sub word line driver SWD is formed of four N-channel metal-oxide semiconductor (NMOS) transistors M1 through M4. The first NMOS transistor M1 has a gate connected to a boosting voltage VPP, and a channel connected between a main word line signal WLE and a first node N1. The second NMOS transistor M2 has a gate connected to the first node N1, and a channel connected between a word line drive signal PXIj and an output node N2 coupled to a sub word line WL. The third NMOS transistor M3 has a channel connected between the main word line signal WLE and the output node N2, and a gate connected to the word line drive signal PXIj. The fourth NMOS transistor M4 has a gate connected to a complementary word line drive signal PXIjB of the word line drive signal PXIj, and a channel connected between the output node N2 and ground voltage VSS.
The main word line signal WLE and the word line drive signal PXIj are activated with a boosting voltage level VPP. During operation of the circuit, when the main word line signal WLE (or main word line selection signal) transitions to high, the first NMOS transistor M1 applies a voltage VPP-Vth (where Vth represents the threshold voltage of the first NMOS transistor M1) to the first node N1. Thereafter, when the word line drive signal PXIj (or sub word line selection signal) transitions to high, the voltage of the first node N1 is boosted up to a higher voltage (2VPP-Vth, for example). The boosting operation (or self-boosting operation) is conducted by coupling capacitance between the gate and drain of the second NMOS transistor M2, as is known in the art. Thus, the second NMOS transistor M2 sufficiently applies the boosting voltage VPP of the word line drive signal PXIj to the output node N2.
However, if the boosting voltage VPP of the main word line signal WLE is applied to the first NMOS transistor M1 after the boosting voltage VPP of the word line drive signal PXIj is applied to the drain of the second NMOS transistor M2, the voltage of the first node N1 is VPP-Vth. At that time, the third NMOS transistor M3 applies a voltage VPP-Vth to output node N2, while the second NMOS transistor M2 applies a lower voltage VPP-2Vth to the output node N2. Thus, the output node N2 is capable of charging up to a maximum voltage of VPP-Vth. The highest voltage at the output node N2, coupled to a cell transistor of memory cell MC, in this instance, is not enough to turn the cell transistor on.
As a result, the main word line signal WLE must be activated before the word line drive signal PXIj is activated, in order to sufficiently charge the sub word line WL up to the boosting voltage. In order to ensure the proper activation order of these signals, a predetermined time interval is established between the activation of the main word line signal WLE and the word line drive signal PXIj. That time interval increases the time required for performing a reliability test for the memory device.
In general, the test time per word line is several microseconds, and, as a result, a significant amount of time is required for testing an entire chip. It would be preferable for the main word lines to be sequentially activated by the activation of the word line drive signal PXIj, in order to reduce the test time. Unfortunately, if this test method is used with the prior art sub word line driver SWD, the voltage applied to the sub word line is defined as VPP-Vth, which is insufficient to turn a cell transistor of a memory cell on. In other words, it is impossible to use this test method to reduce the test time of the prior art memory device.
It is therefore an object of the present invention to provide a sub word line drive circuit for a semiconductor memory device that is capable of reducing the test time of the memory device.
In order to attain the above objects, according to one embodiment of the present invention, a semiconductor memory device includes a plurality of main word lines. A plurality of sub word lines are also included, each of which corresponds to one of the main word lines. A plurality of sub word line drivers are included, wherein each sub word line driver corresponds to one of the sub word lines, and connects the sub word line to the main word line. The sub word line drivers charge the sub word lines up to a boosting voltage regardless of an activation order between a sub word line selection signal and the main word line.
According to another aspect of this invention, a semiconductor memory device includes a plurality of main word lines. A plurality of sub word lines correspond to each of the main word lines. A plurality of sub word line drivers are also included, wherein each sub word line driver corresponds to one of the sub word lines and connects the sub word line to the main word line. Each of the sub word line drivers includes a first transistor for transferring the sub word line selection signal to the sub word line in response to an activation of the main word line and a second transistor connecting the main word line to the sub word line in response to an activation of the sub word line selection signal. In addition, a third transistor connects the main word line to a gate of the first transistor in response to a high voltage, and a fourth transistor connects the sub word line selection signal to a gate of the second transistor in response to the high voltage.
According to various embodiments constructed in accordance with the principles of the invention, the sub word line can be charged up to the boosting voltage regardless of an activation order between the main word line signal and the sub word line selection signal.